RESQUE

Motivation

The RESQUE project is driven by the urgent need to secure critical digital infrastructure in the post-quantum era. As quantum computing threatens to break traditional cryptographic schemes, the adoption of post-quantum cryptography (PQC) has become a priority. However, deploying PQC in real-world environments requires more than algorithmic robustness — it demands resilience against implementation-level threats such as side-channel attacks. These attacks exploit physical leakages (e.g., power consumption, electromagnetic emissions) to compromise even theoretically secure cryptosystems. Our involvement is motivated by the necessity to enhance trust in PQC deployments by systematically addressing these physical vulnerabilities, ensuring that the transition to quantum-resistant algorithms does not open new attack surfaces.

Objectives

The RESQUE project sets out to address the major technical and scientific challenges of deploying post-quantum cryptography in operational environments through four tightly interrelated objectives.

• First, it aims to establish the strongest possible security guarantees by analyzing hybrid authenticated key exchange (AKE) mechanisms and their secure integration into protocols like IKEv2, supported by security proofs.
• Second, the project promotes cryptoagility, ensuring that the architecture can support interchangeable PQC components without requiring redesigns — a critical enabler for long-term maintainability.
• Third, RESQUE prioritizes resistance against side-channel attacks by developing high-assurance countermeasures, including advanced masking techniques and formal verification tools, led by us. The objective is to perform an in-depth review of state-of-the-art side-channel leakage models, attacks, and countermeasures, particularly in the context of signature and key exchange algorithms from the NIST PQC standardization process. We also aim to develop efficient masking techniques tailored to PQC operations, despite their inherent challenges (e.g., data-dependent branching and complex arithmetic). These countermeasures will be formally analyzed, whenever possible, and evaluated by accredited security labs (CESTI). Our ultimate goal would be to deliver secure-by-design implementations suitable for constrained hardware environments such as HSMs, without compromising performance.
• Lastly, the project addresses performance constraints by integrating optimized software implementations and hardware accelerators, ensuring that enhanced security does not come at the cost of throughput or latency, particularly in demanding environments such as high-performance HSMs.

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